1. Field of the Invention
The present invention relates generally to delta-sigma modulation circuits, and more specifically, to a discrete-time delta-sigma analog-to-digital converter having a selectable quantization rate and a ratio between the quantization rate and the sampling rate of the first loop filter stage that is changed with the selectable quantization rate.
2. Background of the Invention
Delta-sigma modulators are in widespread use in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), in which they provide very linear behavior and simple implementation due to the reduced number of bits used in the analog signal comparison. Delta-sigma modulators can be implemented with a high level of control of the frequency distribution of “quantization noise”, which is the difference between the ideal output value of the modulator as determined by the input signal and the actual output of the modulator provided by a quantizer. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable.
For discrete-time delta-sigma modulators in which the digital output rate is selectable, analog anti-aliasing filters that attenuate the input signal at higher image frequencies must typically also be selectable and for lower frequencies of operation, can require large components. Since the sampling rate of the discrete-time integrators employed in the loop filter of the delta-sigma modulator is typically the same as the quantization rate, the aliased images of the input signal occur at a frequency spacing equal to the quantization rate of the delta-sigma modulator. Therefore, when the quantization rate is changed, the anti-aliasing filter must also be changed or the signal-to-noise ratio of the modulator is dramatically compromised if unwanted signal energy exists around multiples of the frequency of the new quantization rate. For example, a discrete time delta-sigma ADC operating at a sampling rate of 3 MHz may require attenuation of the first aliased image, which starts at 3 MHz, by 60 dB in order to meet performance requirements. If a lower quantization rate, for example 500 kHz is then applied, the first alias image occurs at 500 kHz. An exemplary first-order analog resistor-capacitor (RC) anti-aliasing filter has a roll-off slope of 20 dB/decade. Therefore, such an anti-aliasing filter that attenuates a first image at 3 Mhz by 60 dB would yield an attenuation of only 44.5 dB at 500 kHz. Therefore, the corner frequency of the input anti-aliasing filter must typically be adjusted along with the converter quantization rate when the quantization rate is selectable.
However, assuming, for example, that the ADC is an audio ADC having a flat passband from 0 Hz to 20 kHz, providing such an anti-aliasing filter with a 60 dB attenuation at 500 kHz would require a more complex higher-order filter, which requires more power, more circuit area and presents problems with tuning/process variation. Further, since lower quantization rates in an ADC are generally selected to conserve power, such as in battery-operated audio devices under certain conditions, the addition of complex anti-aliasing filters is even more undesirable and may result in no net power savings. Further, in general, as the corner frequency of an internal RC anti-aliasing filter is reduced, the size of the components needed to implement the filter increases, thereby consuming more die area.
Therefore, it would be desirable to provide a delta-sigma modulator that has a selectable quantization rate without the typical consequent reduction in anti-aliasing performance, nor an increase in die area required to implement an internal anti-aliasing filter.